Boundary Scan (also known as IEEE 1149.1 standard or JTAG, JTAG—Joint Test Action Group) is a technique that is extensively used for testing of printed circuit boards (PCBs). Boundary Scan (BS) provides the possibility for an external tester (JTAG control system 401) to take control over board under test (BUT, 402) and use BS-compliant devices (integrated circuits, ICs) 103 of BUT 402 to carry out tests (FIG. 1). For using BS it is required for BUT 402 to contain one or several BS-compliant ICs 103 that form BS test infrastructure. BS is capable for testing of interconnection between BS-compliant components and also testing and configuration of non-BS components (device under test, DUT, 420) that have connections to BS components.
Test access port (TAP) provides access to the test functions implemented in an BS-complient IC according to IEEE1149.1 standard. TAP consists of TAP controller and four dedicated pins: TCK input pin provides the test clock for test logic defined by JTAG standard. Test clock is essential to perform synchronous board test independently from system clock. TMS input pin is used to control test mode according to the TAP controller states. TDI input pin represents the serial data input of test instructions and test data. TDO output pin is the serial test data output that is used to readback the results of test.
All JTAG operations are regulated by TAP controller. It represents a finite state machine that is controlled by TCK and TMS inputs (FIG. 2). TAP controller controls the behavior of test logic and test data flow through BS structures inside the device. In Test-Logic-Reset state 201 the test logic is disabled so that device can operate normally in functional mode. Capture-DR/Capture-IR states are used to capture the input values and for parallel load of them to either data (Capture-DR, 202) or instruction (Capture-IR, 203) register. In Shift-DR/Shift-IR states the values of data (Shift-DR, 204) or instruction (Shift-IR, 205) register are shifted one bit towards TDO with each test clock cycle. At the same time, a new value of TDI pin is shifted in. Shift-DR/IR states are used for shifting new data into registers and reading back the data that was captured in Capture-DR state. In Update-DR(206)/Update-IR(207) states the output registers are updated with the data shifted in Shift-DR/IR state. The update is done in parallel mode, so that all output values are updated synchronously.
BS/JTAG architecture incorporates Instruction Register (IR, 406) to control testing and one or several data registers 302 for feeding test data (FIG. 3). IR 406 is a shift register that holds current BS instruction. This instruction selects the test to be executed or defines which of data registers is accessed in Capture-DR, Shift-DR and Update-DR TAP state. New instruction is shifted into the IR in Shift-IR TAP state. In Update-IR TAP state shifted instruction is latched and becomes active. A process of shifting new instruction into the IR is usually called IR-shift. Data registers 302 are used for transportation of test data to the on-chip or test logic. Similar to the IR behavior, new test data is shifted serially into the data register in Shift-DR TAP state. In Update-DR TAP state the data is latched by test logic. A process of shifting new test data into the data register is called DR-shift.
Boundary Scan Register (BSR, 301) is a key data register in the BS architecture. It is mainly used for testing or programming of devices external to BS component. BSR consists of a number of BS scan-cells 408 connected in serial and thus forming a shift register (scan-chain, scan-path). BS cells are also connected with external pins of IC thus are capable to control or observe signal values on device pins 404.
The known IEEE 1149.1 instructions used for testing are SAMPLE/PRELOAD and EXTEST. SAMPLE/PRELOAD instruction selects the BSR to be accessed by DR-shift and is used to preload test data into BSR while test logic is not operating. EXTEST instruction places BS-device to test mode and makes BSR be active. In test mode the data from output or bi-direction scan-cells of BSR is driven to external pins of device while values on input or bi-direction pins of device are captured into the corresponded cells of BSR.
BS test flow that is based on SAMPLE/PRELOAD and EXTEST instructions is depicted in FIG. 4. At first, SAMPLE/PRELOAD instruction is loaded into BS IC. Then, test data is shifted into BSR. During this step the values of the first test stimuli (test pattern) are set to the corresponding scan-cells of BS IC. After that, EXTEST instruction is loaded into BS IC and it forces IC to start driving the preloaded values of BSR scan-cells to external pins. Next DR-shift of data register is performed to set up the values of new test stimuli (test pattern) and read-back the response obtained in the previous step. The latter step is repeated until all test patterns are executed.
The described procedure is utilized for testing of interconnections between BS-compliant ICs on PCBs. It is also successfully used for testing devices (DUTs) 420 without BS structures inside (including RAM test, FLASH test and programming, etc). In the latter case, the BS-compliant device that is connected to target DUT uses BSR 301 to send the test patterns to DUT and read DUT responses
In order to communicate with target DUT 420 (FIG. 5), JTAG control system 401 sequentially shifts bits (1 bit per test clock cycle) to BSR 301 via TDI 411 and JTAG Interface 405 while TAP controller is in Shift-DR state while IR is loaded with EXTEST instruction. The test data that is intended to be sent to DUT is propagated to the corresponded scan-cells 408 of BSR 301 with each test clock cycle. After the propagation is finished, the data exchange between DUT and BSR is triggered by Update-DR: the test data (stimuli, test pattern) from BSR is applied to DUT via pins 404 and the responses of DUT are captured back into BSR. Next, the responses from DUT are shifted out from TDO 412 in a similar manner: the bits of BSR are shifted along the scan-chain (1 bit per clock cycle) until all the captured values reach TDO.
As the reference, the representation of typical BSR architecture of Field Programmable Gate Array (FPGA) IC is shown in FIG. 6. In this example, BSR contains separate output scan-cell 305, control scan-cell 306 and input scan-cell 307 per each input-output (I/O) pin 404 of FPGA IC. The total length of the BSR is approximated as a number of I/O pins in FPGA device multiplied by 3.
Input scan-cell of BSR is used to capture value on the corresponded pin of FPGA. Control scan-cell is used to switch the direction (output or input) of the pin. If pin is configured as an output, then output scan-cell is used to control the value (0 or 1) driven by the pin. For example, to force pin to drive a signal using BS, the corresponded control cell is loaded with the value that configures this pin for output direction and the corresponded output cell is loaded with the desired value for signal that needs to be driven.
Due to the fixed structure of BSR there are no means that could reduce the number of the test clock cycles needed to perform test data exchange with DUT: the full shift of BSR is always required. However the data supplied to TDI with part of test clock cycles is carrying no useful information for DUT and is shifted in just for the sake of propagation of the actual test data. As a result, the main disadvantage of BS consist in essentially slow speed of test data exchange with DUT caused by the considerable amount of redundant information that need to be supplied to BSR before triggering the application of each test pattern. For example, in FIG. 5 it is needed to shift-in 18 bits of data into BSR 301 (corresponding to the total number of scan-cells 408) however only 4 bits (that correspond to the 4 cells connected with DUT 420) are actually used for test data exchange with DUT.
The other drawback of testing using BSR is the low rate of data exchange with DUT due to the pause between test pattern applications. This pause is induced by necessity to update contents of BSR by shifting in test data of new test pattern. The latter makes impossible to use BSR for testing of DUT that requires high rate of test application (i.e. small or no delay between two consecutive test patterns).
The purpose of the present invention is to overcome the abovementioned drawbacks of BS.
Known extensions to BS technique are also described in several patent documents. U.S. Pat. No. 7,248,070 and U.S. Pat. No. 7,550,995 describe method and system for using boundary scan in a programmable logic device (PLD). U.S. Pat. No. 6,925,583 and U.S. Pat. No. 7,047,467 describe structure and method for writing from a JTAG device with microcontroller to a non-JTAG Device. U.S. Pat. No. 6,594,802 describes method and apparatus for providing optimized access to circuits for debug, programming, and test. The presented architectures cannot be implemented into programmable device (PLD or FPGA) in such a form that will match any possible types of DUT or the position of DUT relatively to pins of PLD/FPGA. This means, that for each new test case, re-implementation of the architecture is required.
Patent application US2005204229 describes boundary scan tester for logic devices. This solution requires de-compressor to be implemented in electronic device along to BSR. This blocks the usage of the technique in already existing devices that do not have decompression structures inside. The speed-up is fully depending on the potential compression ratio of the incoming data that may vary.
U.S. Pat. No. 5,991,908 describes boundary scan chain with dedicated programmable routing. The described architecture is targeted to mask-programmable devices only. The disadvantages are that the architecture cannot be implemented into PLD or FPGA device in a such form that will match any possible types of DUT or the position of DUT relatively to pins of PLD/FPGA. This means, that for each new test case, re-implementation of the architecture is required.
U.S. Pat. No. 6,314,539, boundary scan register cell with bypass circuit, presents a method that supplements BSR register with for optimized test access. It does not contain methods that can be applied to existing programmable logic devices without changes in their structure. It also does not provide any system or method for optimized test application.